Devices having high-speed operating characteristics, operating in response to high clock frequencies, and/or requiring long transmission lines may exhibit undershoot signal reflections and/or undesired transmission line effects.
If a signal with a “0” voltage level travels down a bus or a long transmission line, the signal may then inverted to a “5” voltage level, and an impedance mismatch between a receiver circuit and the bus or the transmission line may be left uncorrected so that, reflection may occur on the transmission line or at one or both ends of the bus. Because of the reflection, the signal may take a long time to stabilize after the voltage level transition from “0” to “5” volts.
High-speed semiconductor devices may have reduced clock signal rise and fall times. If the rise and fall times are shorter than 2.5 times a delay in the transmission line of the clock signal, the clock signal received by the receiver circuit may be significantly distorted and may be unusable as a valid signal. Such a problem may be referred to as ringing. In an attempt to reduce distortion and reflection, impedance matching may be implemented for electromagnetic wave transmission.
FIG. 1 is a circuit diagram illustrating a known termination circuit. Referring to FIG. 1, termination resistors R1 and R2, a PMOS transistor MP, and an NMOS transistor MN are serially connected between a supply voltage VDD and a ground voltage VSS. The PMOS transistor MP has a gate connected to the ground voltage VSS, and the NMOS transistor MN has a gate connected to the supply voltage VDD. In a termination circuit 100 of FIG. 1, impedance matching is implemented in parallel.
An impedance of a transmission line (to which an input signal INS is applied) is matched with impedances of the termination resistors R1 and R2. The waveform of a voltage level at the first node N1 (between the termination resistors R1 and R2) may show reduced distortion compared to the case when the termination resistors R1 and R2 are not connected with the PMOS transistor MP and the NMOS transistor MN.
In the termination circuit 100, however, the PMOS transistor MP and the NMOS transistor MN may be turned on all the time, and a path for current flow may be formed from the supply voltage VDD toward the ground voltage VSS. Thus, power consumption increases during transmission of the input signal INS may make it undesirable to use the termination circuit 100 in a low power-consumption device.
FIG. 2 is a circuit diagram illustrating another known termination circuit 200. Referring to FIG. 2, the termination resistors R1 and R2, the PMOS transistor MP, and the NMOS transistor MN are serially connected between the supply voltage VDD and the ground voltage VSS. The PMOS transistor MP has a gate connected to an inverter I1 that inverts the voltage level of the input signal INS and applies the inverted voltage level to the gate of the PMOS transistor MP. The NMOS transistor MN has a gate connected to an inverter I2 that inverts the voltage level of the input signal INS and applies the inverted voltage level to the gate of the NMOS transistor MN. In the termination circuit 200 of FIG. 2, impedance matching is implemented in parallel.
When the inverter I1 inverts the voltage level of the input signal INS during/after a transition from low to high, the PMOS transistor MP may be turned on. Then, a path for current flow can be formed between the first node N1 and the supply voltage VDD.
The voltage level at the first node N1 can be increased by the supply voltage VDD and may reach the level of the supply voltage VDD or ground voltage VSS. Thus, a relatively long time may be needed to invert the voltage level at the first node N1 from high to low and vice versa.
FIG. 3 is a waveform of the voltage level at the first node N1 of the termination circuit 200 of FIG. 2. Referring to FIG. 3, when the voltage level of the input signal INS is inverted to a high voltage level, the waveform of the voltage level at the first node N1 is also inverted a high voltage level. However, when the PMOS transistor MP is turned on, distortion may occur at the first node N1, as shown by the waveform in FIG. 3. In other words, the termination circuit 200 of FIG. 2 may provide lower power consumption compared to the termination circuit 100 of FIG. 1, but distortion may occur at the first node N1.
FIG. 4 is a circuit diagram illustrating still another known termination circuit 400. Referring to FIG. 4, the PMOS transistor MP, the NMOS transistor MN, and termination resistors R3 and R4 are serially connected between the supply voltage VDD and the ground voltage VSS. A first capacitor C1 is connected between the gate of the PMOS transistor MP and the first node N1 (which functions as a connection point of the termination resistors R3 and R4). A resistor R1 is connected between the supply voltage VDD and the gate of the PMOS transistor MP. A second capacitor C2 is connected between the gate of the NMOS transistor MN and the first node N1, and a resistor R2 is connected between the ground voltage VSS and the gate of the NMOS transistor MN.
The PMOS transistor MP and the NMOS transistor MN can be turned off using the first capacitor C1 and the second capacitor C2. If the input signal INS is input at a high voltage level, the second capacitor C2 may be charged and the NMOS transistor MN may be turned on for a moment, while the PMOS transistor MP is turned off. Electrical charges in the second capacitor C2 may dissipate through the ground voltage VSS, and then the NMOS transistor MN may be turned off. Thus, termination of the input signal INS may be inaccurately performed.
FIG. 5A is a graph showing impedances of the termination transistors R3 and R4 of the termination circuit 400 of FIG. 4. FIG. 5B is a waveform of the voltage level at the first node N1 of FIG. 4.
Referring to FIG. 5A, the impedances of the termination resistors R3 and R4 may be nearly infinite at time points immediately before the signal INS is input and after the NMOS transistor MN is turned on and off by the input signal INS.
Because the impedances of the termination resistors R3 and R4 may have to be maintained level with respect to a specific value to reduce ringing or reflection, however, the termination circuit 400 of FIG. 4 may not accurately perform termination of the input signal INS.
Referring to FIG. 5B, the waveform of the voltage level at the first node N1 may exhibit high overshoot and/or undershoot when the voltage level of the input signal INS transitions from low to high and/or from high to low. Known termination circuits may consume high power and/or distort signals.